In the art of semiconductor integrated circuit devices capable of the high-speed operation and high driving capacity of a bipolar transistor and the small power consumption of a CMOS, it is conventionally known to form the bipolar transistor and the CMOS on the same chip substrate in a BiCMOS structures.
However, the need for yet higher speeds and for yet smaller power consumption and size are not yet completely satisfied. Accordingly, the inventor of the present invention has disclosed an improvement to the conventional methods in Japanese Patent Application No. 09-171657 which is related to present invention but which is not believed to be prior art.
This related invention will be explained with reference to FIGS. 1A to 1H.
First, in FIG. 1A, an element isolation oxide film 107 and a first oxide film 133 are formed in a P-type silicon substrate 101 by the LOCOS (Local Oxidation of Silicon) isolation method and the STI (Shallow Trench Isolation) method which are generally known.
Then, as shown in FIG. 1B, a first P-type well region 102 is formed in the NMOS forming region by implanting, for example, boron ions at an energy of 350 keV and a concentration of 5.times.10.sup.13 cm.sup.-2. First N-type well regions 106 are formed in the PMOS forming region and the collector region of a bipolar transistor by implanting phosphorus ions at an energy of 700 keV and a concentration of 5.times.10.sup.13 cm.sup.-2.
As shown in FIG. 1C, after removing the first oxidation film 133, a first insulating film 108 having a thickness of 5 to 10 nm is formed on the surface of substrate 101. The first insulating film 108 comprises a gate oxide film. Then, for example, boron or BF.sub.2 ions are implanted at an energy of 10 to 50 keV and a concentration of 1.times.10.sup.13 to 5.times.10.sup.14 cm.sup.-2 to form a P-type base region 109. An emitter contact 110 and a collector contact 126 are opened, and then first conductive polysilicon 112 is grown to a thickness of 150 to 400 nm.
Significantly, as shown in FIG. 1D, gate electrodes 113, 141 and an emitter leading electrode 114 are formed from first polysilicon 112 by anisotropic etching using a mask made of photoresist or the like. An etch using the same mask and the first insulating film 108 as masks forms a collector trench 124, and the mask is thereafter removed. These types of etching can be continuously performed under the same condition or performed in a plurality of steps by dividing the etching into several stages.
Next, as shown in FIG. 1E, an N-type LDD (Lightly Doped Drain) layer 120 and a P-type LDD layer 121 are formed. Side walls 119 are then formed on the walls of the gate electrodes 113, 141, emitter leading electrode 114, and collector trench 124 respectively by anisotropic etching.
Then, in FIG. 1F, a thin oxide film 132 having a thickness of 5 to 20 nm is formed. An N.sup.+ -type diffusion layer 128 at the bottom of the collector trench 124 and N.sup.+ -type source-drain 122 of the NMOS device are formed by implanting ions of an impurity such as phosphorus or arsenic. This implantion of N-type ions also makes gate electrode 113 of the NMOS device into an N-type gate electrode. P.sup.+ -type source-drain 123 and P.sup.+ -type graft base 116 of the PMOS device are formed by implanting ions of an impurity such as boron or BF.sub.2. This implantation of P-type ions also makes gate electrode 141 of the PMOS device into a P-type gate electrode.
Note that an impurity is introduced into the emitter leading electrode 114 by implanting ions of an impurity such as phosphorus or arsenic when forming the N.sup.+ -type source-drain 122 or by introducing the impurity by adding another process step.
With reference to FIG. 1G, surfaces of the gate electrodes 113, 141, emitter leading electrode 114, N.sup.+ -type diffusion layer 128 at the bottom of the collector trench 124, N.sup.+ -type source-drains 122, P.sup.+ -type source-drain 123, and P.sup.+ -type graft base 116 are transformed into silicide through a conventional method by using a metal such as titanium, cobalt, or nickel to form a silicide layer 125.
In FIG. 1H, a layer insulating film 127 formed with, for example, a 5 nm-thick oxide film (TEOS-SiO.sub.2 film) and a 800 nm-thick BPSG (boron-phosphorus-silicate-glass) is grown. The film 127 is subjected to RTA (rapid thermal annealing) at 1,050.degree. C. for 5 to 15 sec or oven annealing at 900.degree. C. for 20 to 30 min to form an emitter diffusion layer 117. Thereafter, a contact is opened to form a contact plug 129 through a barrier metal (not illustrated) and then, metallic wiring 130 is formed.
However, the first problem with this process is that the mask made of photoresist or the like and the first insulating film 108 are respectively masked and etched when forming the collector trench as shown in FIG. 1D. This reduces the thickness of the first insulating film 108 and reduces its effectiveness as a mask.
There is also a second problem with this process. When a wiring layer is shared by a gate electrode and an emitter leading electrode in a BiCMOS fabrication method, there is no problem if a P-channel MOS gate electrode and an N-channel MOS gate electrode are both formed from N type polysilicon. However, when forming a P-type gate electrode, referred to as a PN gate, on a P-channel MOS and an N-type gate electrode on an N-channel MOS, and when using an emitter electrode and a wiring layer in common, it is necessary to implant P-type and N-type impurities separately from each other in the polysilicon constituting the gate electrode and the emitter leading electrode. This increases the number of man-hours and decreases the number of degrees of freedom in the fabrication process.